A Self-Cascoding CMOS Circuit for Low-Power Applications

A self-cascading CMOS circuit for operation in weak inversion is presented. The self-cascoding MOSFET circuit has been shown to exhibit greater than twentY:'fold increase in the output resistance, without paying virtually any penalty in real estate and power consumption. The circuit has been used to increase the gain in the front stage of operational amplifiers, and to obtain improved performance from analog current copier circuits. L INTRODUCTION A conventional cascode circuit is shown in fig. 1. The cascade circuit consists of two transistors (Mm, Me) connected in series and are usually biased to operate in saturation. The bias level of the cascade transistor <Me) is usually generated on-chip at the cost of increased power and real-estate. Furthermore, the performance of certain class of cascode circuits called regulated cascade circuits depends critically on the bias currents [1]. There are two main reasons for the use of cascode circuits [2]. First, the output resistance of a cascode circuit is higher than that of an ordinary MOSFET. Secondly, the input capacitance can be kept low due to reduced miller effect. In several applications, such as current memory circuits [3, 4] and capacitive transimpedance amplifiers, low input capacitance may not be required. However, the availability of large output resistances is important to the operation of these circuits. Specifically, increased output resistance translates to higher gain in amplifiers and lower error in current copier circuits. In this brief, an alternate cascode circuit conslstmg of a double gate MOSFET called self­ cascoding FET (SCFET) is presented. The SCFET features increased output resistance compared to a single FET biased under similar operating conditions and is intended for use in applications where low­ power and small real-estate are important. The cell design is simple, and unlike existing cascode